Article ID: 000074282 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why are FIFO full status bits in 10GBASE-R IP core swapped?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In the 10GBASE-R PHY IP core version 10.1 and earlier, the TX_FIFO_FULL and RX_FIFO_FULL status bits are swapped.

    Affected Configurations

    This issue affects Stratix® IV and Stratix V implementations of the 10GBASE-R PHY.

    Solution Status

    This issue is fixed in the 10GBASE-R PHY IP core version 11.0.

    Resolution

    The workaround is to note that for the 10.1 and earlier release RX_FIFO_FULL is actually stored as bit 3 of address 0x82 and TX_FIFO_FULL is stored as bit 4 of address 0x82.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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