Article ID: 000074280 Content Type: Troubleshooting Last Reviewed: 01/23/2023

What is the correct guideline for sharing VCCIO_UIB_(BL,TL) , VCCIO_SDM, VCCIO and VCCIO3V supplies when using Intel Stratix 10® MX devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in  Intel® Stratix® 10 Device Family Pin Connection Guidelines  version 2020.04.20 version, Table-47 and Table-48 titled Power Supply Sharing Guidelines for Intel Stratix® 10 MX (E-Tile) show VCCIO_UIB_(BL,TL) , VCCIO_SDM, VCCIO and VCCIO3V sharing the same voltage by mistake.

    VCCIO_UIB_(BL, TL) should be 1.2V, VCCIO_SDM should be 1.8V. VCCIO and VCCIO3V is variable. VCCIO, VCCIO3V and VCCIO_SDM can be shared with 1.8V from the same regulator when they are all 1.8V.

    Resolution

    This problem is resolved since the 2020.10.23 version of the Intel® Stratix® 10 Device Family Pin Connection Guidelines .

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA