Article ID: 000074279 Content Type: Troubleshooting Last Reviewed: 03/24/2020

Why do the Intel® MAX® 10 FPGA pin numbers K22 and K21 on the Intel MAX 10 FPGA 10M50 Evaluation Kit not support the LVDS IO standard?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a known problem with the MAX 10 FPGA 10M50 Evaluation Kit,  it is incorrectly stated that the Intel® MAX® 10 FPGA pin numbers K22 and K21 can be used as differential clock inputs. 

    However, these pins cannot be used as a differential clock inputs. 

     

    Resolution

     This information will be corrected in a future version of the MAX 10 FPGA 10M50 Evaluation Kit User Guide.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs