Why does triggering reconfiguration fail after programming flash through Parallel Flash Loader FPGA IP or Parallel Flash Loader II FPGA IP when using JAM/JBC files?

Due to a problem with JAM/JBC files generated in Quartus® Prime Software version 20.1 and earlier, if Passive Serial (PS), Fast Passive Parallel (FPP) or AVST configuration scheme is realized with Parallel Flash Loader FPGA IP (PFL) or Parallel Flash Loader II FPGA IP (PFL II), reconfiguration triggering fails after programming the flash using JAM/JBC files. 

Before triggering reconfiguration through PFL IP or PFL II IP or toggling the configuration target FPGA's nconfig pin, you need to execute the action of "Auto Detect" through Quartus® Prime Programmer. If you cannot access Quartus® Prime Programmer,  contact Intel Premier Support for further support.