No. Table 2. Configuration/JTAG Pins in Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines version 2017.12.15 has the following guideline for CONFIG_SEL pin:
Connect a weak 10-KΩ pull-up or weak 10-KΩ pull-down to this pin externally during the power-up phase.
When you use dual configuration image mode, you need to connect a weak pull-up resistor or a weak pull-down resistor to the CONFIG_SEL pin externally to select one of two configuration images during the power-up phase.
But when you do not use dual configuration image mode, you do not need to connect a weak pull-up resistor or a weak pull-down resistor to the CONFIG_SEL pin. In single configuration image mode, image 0 is loaded after power-up without sampling the CONFIG_SEL pin.
Refer to the latest document, Table 2. Configuration/JTAG Pins in Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines.
