No. Even if the Intel® Quartus® Prime Software does not issue an error, you cannot use higher PLL VCO frequency than the PLL specifications for Cyclone® V devices.
Due to a problem with the Intel Quartus Prime Software, the fitter might issue no error even if the PLL VCO frequency is higher than the specifications.
The maximum PLL VCO frequency for Cyclone V FPGA -7 and -8 speed grades is 1300 MHz. When the VCO frequency is higher than 1300 MHz, but the output clock frequency is not higher than 1300 MHz in those devices, the fitter issues no error. When the output clock frequency is higher than 1300 MHz in those devices, the fitter issues an error.
Example case 1
Device : Cyclone V FPGA -7 or -8 grades
Altera PLL IP parameter editor settings
Reference : clock 8 MHz
Output clocks
outclk1 : 25 MHz
outclk2 : 64 MHz
M counter : 200
N counter : 1
C counter-0 64
C counter-1 25
The VCO frequency is 1600MHz for this parameters, but the fitter issue no error.
Example case 2
Device : Cyclone V -7 or -8 grades
Altera PLL IP parameter editor settings
Reference : clock 10 MHz
Output clocks
outclk0 : 400 MHz
outclk1 : 1,600 MHz
M counter : 160
N counter : 1
C counter-0 : 4
C counter-1 : 1
The VCO frequency is 1,600 MHz for this parameters and the outclk1 frequency is 1,600 MHz. The fitter issues an error for the outclk1 frequency.
When you use Cyclone® V FPGA -7 or -8 speed grade, check manually if the PLL VCO frequency is higher than the PLL specifications or not in the fitter report. If the PLL VCO frequency is higher than the PLL specifications, change the parameters of the PLL to keep the PLL VCO frequency within the specifications.
You can see the PLL VCO frequency of the filter report in your design project using the following steps:
- Open menu Processing > Compilation Report.
- Open the Resource Section under the Fitter folder in the Table of Contents panel of the Compilation Report window.
- Choose PLL usage Summary under Resource Section.