Why do output clocks of the IOPLL Intel® FPGA IP have incorrect phase shifts with respect to the reference clock in simulation in Intel Arria® 10 and Intel Cyclone® 10 GX?

Due to a problem of the simulation model generated by Intel® Quartus® Prime software, output clocks of the IOPLL Intel FPGA IP may have incorrect phase shifts with respect to the reference clock in simulation in Intel Arria® 10 and Intel Cyclone® 10 GX.  The output clocks of the IOPLL Intel FPGA IP hardware have correct phase shifts according to the phase shift settings in the IP parameter editor. 

Perform hardware verification when checking phase shifts of output clocks of the IOPLL Intel FPGA IP in Intel® Arria® 10 and Intel Cyclone® 10 GX.