Article ID: 000074230 Content Type: Error Messages Last Reviewed: 12/11/2018

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Environment

FPGA Intellectual Property

DDR3 SDRAM Controller with UniPHY Intel® FPGA IP

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Description

You may see the critical warning above during the fitter stage when compiling the UniPHY-based memory controller IP.

Resolution

You may safely ignore this critical warning message.

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