Article ID: 000074224 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I see timing violations and ignored clock constraint warning messages in my UniPHY-based DDR3, DDR2, QDRII/ , or RLDRAM II memory controller design?



There is a known issue with the SDC timing constraints file generated by UniPHY-based DDR3, DDR2, QDRII/ and RLDRAM II memory controller IP. The create_generated_clock constraints used in this SDC file are not compatible with the derive_pll_clocks function call. If your design contains another SDC file that utlizes the  derive_pll_clocks function, the UniPHY PLL clock constraints may be ignored by TimeQuest and lead to memory interface timing violations.

This issue affects all designs using UniPHY-based memory controller IP from Quartus® II software versions 10.0 SP1 and earlier. To workaround the issue in these versions of Quartus II software, ensure that the UniPHY IP generated SDC is sourced first (before any other SDC file in the design). This can be done by ensuring the QIP file is the first design file referenced in the "Add Files to Project" setting window and/or the QSF file.

This issue has been fixed in Quartus II software version 10.1. Regenerate your UniPHY IP instances to resolve the SDC compatability issue.

Related Products

This article applies to 4 products

Stratix® IV GX FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® III FPGAs



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