Article ID: 000074182 Content Type: Troubleshooting Last Reviewed: 10/10/2019

What is the state of General Purpose I/Os (GPIOs) after the periphery image is loaded when Configuration via Protocol (CvP) is used in Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In Intel® Stratix® 10 devices, when Configuration via Protocol (CvP) is used, the state of General Purpose I/Os (GPIOs) is tri-stated with weak pull-up after Power-On reset (POR) and until the core image is loaded. Once the core image is loaded the state of the GPIOs will be according to the loaded design.

    Resolution

    This information is scheduled to be added in a future release of the Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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