You may experience this synthesis problem in Stratix designs if you have a process or always block with an asynchronous set (aset, at least one non-zero bit), as well as a synchronous load (sload) or synchronous clear (sclr). If your design contains an aset along with an sload or sclr signal, you may find that your sload or sclr result is inverted. For example, a synchronous loadable downcounter with an asynchronous preset signal might exhibit this failure. Since NIOS designs contain these types of logic configurations, your NIOS design may not boot correctly in a Stratix device.
To avoid this problem, synthesize your design using LeonardoSpectrum 2002d (released late September 2002 with the Quartus® II software version 2.1 SP1) or later. If the failure occurs in your own HDL (hardware description language) code, you can work around the problem in LeonardoSpectrum 2002c by avoiding these specific combinations of synchronous and asynchronous control signals for Stratix. Use an asynchronous clear (aclr) signal instead of aset, or avoid mixing the use of aset with a synchronrous load or clear control signal.