Article ID: 000074101 Content Type: Troubleshooting Last Reviewed: 08/15/2012

Why is my multi-dimensional port split into individual single-bit ports in the gate-level simulation netlist?

Environment

    Quartus® II Subscription Edition
    Simulation
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Description Due to a limitation in the Quartus® II software, for designs written in AHDL with Verilog HDL specified as the output simulation netlist format, multi-dimensional ports are split into individual single-bit ports in the output netlist.
Resolution

To work around this limitation, generate your output simulation netlist in VHDL instead of Verilog HDL.

 

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