Description
When the eSRAM Intel® Stratix® 10 FPGA IP is included in your design, you might see an incorrect data or all "zero" data in some channels.
Resolution
To work around this problem, include the Reset Release Intel® FPGA IP and connect the nINIT_DONE output signal from the Reset Release Intel FPGA IP to the input signal c<channel_number>_sd_n_0 of the eSRAM Intel Stratix® 10 FPGA IP.
This information is included in the Intel Stratix 10 Embedded Memory User Guide.