Article ID: 000074061 Content Type: Troubleshooting Last Reviewed: 11/18/2024

Why are the signals in the Signal Tap Logic Analyzer which are actually connected displayed in red?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 18.1 and earlier, the signals in the Signal Tap Logic Analyzer may be displayed in red, even though they are actually connected to the internal nodes during compilation.

    Resolution

    To check whether the signals in the Signal Tap Logic Analyzer are correctly connected, go to the Compilation Report > Synthesis folder > In-System Debugging report. The actual connection column reports the real connection after compilation.

    This problem is fixed starting with the Quartus® Prime Pro Edition Software version 19.3.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs