Article ID: 000074051 Content Type: Install & Setup Last Reviewed: 08/30/2023

The data ports do not connect to ALTDDIO registers, but the data rate is set to double the data rate.

Environment

  • Intel® Quartus® Prime Standard Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.1 and earlier, you may see this error message if you launch the I/O Timing Constrainer in the NIOS® II command shell. This is because you have a soft LVDS Intel® FPGA IP in your design, and the I/O Timing Constrainer failed to run at double the data rate.

    Resolution

    To work around this problem, write the constraint in the <project>.sdc instead of using the I/O Timing Constrainer in the NIOS® II command shell.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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