Error (10170): Verilog HDL syntax error at source.sv(7) near text: "XXX"; expecting ")

Due to a problem in the Intel® Quartus® Prime Standard edition software version 19.1 you will observe this error when you use instantiated typedef enum in a module with an explicit nettype. 

To work around this problem, remove the explicit nettype from the module definition. If the Verilog source is part of a library and cannot change, use VERILOG_MACRO with ifdef statement to contain the Verilog code that is handled by the Intel® Quartus® Prime Standard edition software. The name of the VERILOG_MACRO can be defined in the Intel Quartus Setting File (.qsf) with the following assignment:

set_global_assignment -name VERILOG_MACRO "<USER_DEFINED>=1"