Article ID: 000074007 Content Type: Error Messages Last Reviewed: 11/23/2016

Warning (332088): No paths exist between clock target "*|altpcie_a10_hip_pipen1b|wys|core_clk_out" of clock "dut|wys~CORE_CLK_OUT" and its clock source. Assuming zero source clock latency.

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime software versions 16.1 and earlier, you may see this warning when compiling designs containing the Arria® 10 Hard IP for PCI® Express.

    Resolution

    This warning can be safely ignored.

    The warning is scheduled to be removed from a future release of the Arria 10 Hard IP for PCI Express.

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