Why does the Intel® Arria® 10 Transceiver Native PHY IP multi channels design with 10G BASE-R preset encounter functional fail ?

Due to a problem with the Intel® Arria® 10 Transceiver Native PHY IP in the Intel® Quartus® Prime standard edition software version 16.1 onwards, multiple channels design generated with 10G BASE-R preset will contain wrong rx_control port mapping.

This problem only occurs in Transceiver Native PHY IP launched in Qsys (now Platform Designer) while it doesn't impact Transceiver Native PHY IP launched with IP Catalog.

Example explanations as below :

1. Transceiver NativePHY IP rx_control port is 20 bits width port. The signal name is RX_control bit[19:0]
2. RX_control port encoding mapping for 10GBASE-R preset is using first 8 bit only which is bit[7:0] while bit[19:8] is left unused.
3. Hence if 2 Transceiver channels are enabled, RX_control for ch0 is bit[19:0], ch1 is bit[39:20]
   • ch0 unused bit is bit[19:8] while used bit is bit[7:0] 
   • ch1 unused bit is bit[39:28] while used bit is bit[27:20] 
4. Qsys Transceiver NativePHY IP ch1 connects rx_control wrongly to bit[135:128] instead of bit[27:20].
5. Correct address offset for rx_control should be 20 instead of 128

User can edit the following TCL script to work around the problem.

1. Looks for interface.tcl in the Intel Quartus Prime software installation folder
   • ip\altera\alt_xcvr\altera_xcvr_native_phy\altera_xcvr_native_vi\tcl\interfaces.tcl
2. Search for "proc ::altera_xcvr_native_vi::interfaces::elaborate_rx_control" in the TCL script 
3. Edit and correct below coding
   • set add_offset [expr 128 * $PROP_IFACE_SPLIT_INDEX] should be corrected to set add_offset [expr 20 * $PROP_IFACE_SPLIT_INDEX]
     

This problem will be fixed in a future version of the Intel Quartus Prime Standard edition software and Pro edition software.