Article ID: 000073971 Content Type: Product Information & Documentation Last Reviewed: 10/10/2018

How do I reduce the number of “informational” functional simulation messages produced by the Intel® Stratix® 10 transceiver models?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

During functional simulation of the Intel® Stratix® 10 transceiver, a number of “informational” messages are produced by the model.

Resolution

To reduce the number of “informational” messages produced by the transceiver simulation model, add the following option to the simulator’s compilation/elaboration line for the transceiver IP’s top-level
instance:

" define DISABLE_PARAM_INFO"

Related Products

This article applies to 4 products

Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 SX SoC FPGA
Intel® Stratix® 10 TX FPGA

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