Article ID: 000073960 Content Type: Troubleshooting Last Reviewed: 08/20/2018

Why might I see an occasional high Bit Error Rate (BER) after power-up or user-mode calibration of my Intel® Arria® 10 or Cyclone® 10 GX device RX simplex transceiver?


  • Intel® Quartus® Prime Pro Edition

    Due to a bug in the Intel Arria 10 or Cyclone 10 GX device calibration code, you may see a high BER after power-up or user-mode calibration of an RX simplex transceiver, when the corresponding unused transmitter is preserved with one of the following Quartus® Prime Settings File (QSF) assignments.


    Global preservation QSF assignment

    set_global_assignment –name PRESERVE_UNUSED_XCVR_CHANNEL ON

    Per-pin preservation QSF assignment

    set_instance_assignment –name PRESERVE_UNUSED_XCVR_CHANNEL ON –to <pin name>


    The simplex receiver channel may not be calibrated correctly if its corresponding unused transmitter is preserved. Simplex receiver channels whose corresponding transmitter are not preserved are calibrated correctly.


    You can use one of the following methods to work around this problem.

    • In cases where the unused transmitter will never be used, and does not need to be preserved, you can remove the QSF assignment for the corresponding transmitter pin.
    • In cases where the unused transmitter may be used in the future and preservation is required, you can instantiate a minimum datarate, dummy simplex transmitter corresponding to the used simplex receiver. You can set a static 0x00 pattern on the Tx parallel port, and select minimum VOD.
    • This problem will be fixed in a future version of the Quartus Prime software.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs



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