Why can HPS GPIO on Intel® Stratix®10 SoC device still be controlled by user software even though these signals are not connected to device pin in design?

HPS GPIO is configured by the HPS software during the booting-up process as long as HPS GPIO is enabled in the Platform Designer system. They are active after being configured by FSBL software and can be controlled by user software.  Intel® Quartus® Prime Edition Software does not generate a warning or error if these signals are enabled in the Platform Designer system but not connected to device pins in the design. 

Please do not enable these signals in Platform Designer system which are not connected to device pins in the design.