Article ID: 000073872 Content Type: Troubleshooting Last Reviewed: 12/14/2022

Why can't the interface clock frequency be set to a value between 137.5MHz to 149.9MHz for the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP when using quarter rate mode?

Environment

  • PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to the PLL VCO setting limitation, the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP doesn’t support the frequency range between 137.5MHz to 149.9MHz when using quarter rate mode. 

    Resolution

    There is no workaround to resolve this problem.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs