Why don't the IOPLL output clocks operate as expected when using Advanced Mode reconfiguration following table 18 in the Intel Agilex® 7 FPGA Clocking and PLL User Guide?

Due to a problem in the Intel Agilex® 7 FPGA Clocking and PLL User Guide (UG-20216) version 2021.06.21, the address map for C1-C7 counters in table 18 is incorrect.

Therefore, if you follow the address map in table 18, the IOPLL output clocks will not output the correct clocks as expected.

To work around this problem, follow the address setting and C Counter Mapping as shown in the following table.

This problem is fixed starting with the release of the Intel Agilex® 7 FPGA Clocking and PLL User Guide version 2022.11.09.