Article ID: 000073855 Content Type: Troubleshooting Last Reviewed: 10/25/2021

Why does FPGA configuration fail from Linux / u-boot fail on Intel® Stratix® 10 SX devices when I use phase 2 bitstreams generated from different Intel® Quartus® Prime Software projects?

Environment

    Intel® Quartus® Prime Pro Edition
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Critical Issue

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 20.1 and earlier,  FPGA configuration from Linux / u-boot as part of an HPS first boot flow may fail for designs targeting Intel® Stratix® 10 SX devices if Phase 1 and Phase 2 bitstreams are generated from different Intel® Quartus® Prime Pro Edition Software projects.

The following errors may be seen:

Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: ERROR - giving up - SVC_STATUS_RECONFIG_ERROR

Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: s10_ops_write not all buffers were freed

fpga_manager fpga0: Error while writing image data to FPGA

Resolution

To resolve this problem in the Intel® Quartus® Prime Pro Edition Software v19.1: 

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software v19.1. Download and install the following Patch 0.13:

After installation of the patch follow the steps in the Readme file.

To resolve this problem in the Intel® Quartus® Prime Pro Edition Software versions 19.2, 19.3, and 19.4:

  • The INI setting documented in 19.1-0.13 readme must be in place

To resolve this problem in the Intel® Quartus® Prime Pro Edition Software versions 20.1 and later:

  • The following global assignment must be added to the <project name>.qsf  settings file
    • set_global_assignment -name INI_VARS "asm_constant_hpsio_hash = on"

This problem is scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software.

 

Related Products

This article applies to 2 products

Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 SX SoC FPGA

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