Article ID: 000073821 Content Type: Error Messages Last Reviewed: 03/19/2023

Error (272006): Port addressstall_a is connected in the ALTDPRAM megafunction -- MLAB block for device family Stratix V of the ALTDPRAM megafunction cannot use wraddrstall signal


  • Quartus® II Subscription Edition

    The Quartus® II software might generate this error when compiling a design that targets a Stratix® V device. This problem might occur if your design contains a memory megafunction generated with the parameter editor in the Quartus II software versions 12.0 SP1 and earlier. The error occurs if the memory has the wr_addressstall port connected and is implemented using MLAB resources.


    To work around this problem, either change the memory type to M20K or disable the wr_addressstall port in the parameter editor.

    This problem is fixed starting with the Quartus® II software version 14.0 where the wr_addressstall port can be used with Stratix V MLAB memory blocks but only when the Read-During-Write option is set to Old memory contents appear.

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA