Article ID: 000073811 Content Type: Troubleshooting Last Reviewed: 08/19/2015

When using the Arria 10 PCI Express IP core in Avalon-ST mode, why do I see a 1 clock latency between tx_cred_fc_sel and tx_cred_hdr_fc/tx_cred_data_fc outputs in simulation, but a 2 clock latency in actual hardware?


  • Quartus® II Subscription Edition
    Description When using the Arria® 10 HIP for PCI Express® in Avalon®-ST mode you will see a latency difference between simulation and hardware. This behavior is due to a problem in the Quartus® II software.  The correct behavior is that seen in hardware, which is 2 pld_clk cycles of delay between the assertion of tx_cred_fc_sel and the appearance of coresponding data on tx_cred_hdr_fc and tx_cred_data_fc.

    To work around this problem, add a small delay to the tx_cred_fc_sel signal in your testbench.  For example:

    assign #1 tx_cred_fc_sel-to-core = tx_cred_fc_sel;

    This issue is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA