Article ID: 000073792 Content Type: Error Messages Last Reviewed: 06/29/2014

Error (175001): Could not place LC_PLL_CHANNEL_CLUSTER

Environment

  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description If you implement the Low Latency PHY with channel bonding and fb_compensation mode in Quartus® II 12.1 for Stratix® V devices, and need to reconfigure the Tx PLL, you may get the fitter error above.
    Resolution

    You should add XCVR_TX_PLL_RECONFIG_GROUP assignments for the tx_pll of each channel to enable Tx PLL merging.

    You can find the tx_pll name in post-synthesis results.

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