Article ID: 000073782 Content Type: Troubleshooting Last Reviewed: 10/02/2014

RapidIO IP Core Port-Enable Using Register Field PORT_DIS Does Not Function Correctly

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    You should be able to use the PORT_DIS field in bit [23] of the RapidIO IP core Port 0 Control CSR at offset 0x15C to disable and re-enable the IP core’s RapidIO link receiver functionality. Setting this register bit to the value of 1 should disable the receiver functionality, and setting it to the value of 0 should re-enable the receiver and cause it to reinitialize.

    However, the register bit does not function correctly. If you turn off the IP core receiver by setting the value of this register bit to 1, and then attempt to turn the receiver back on by setting the value of the register bit to 0, the receiver remains turned off and the RapidIO IP core receiver hangs.

    Resolution

    This issue has no workaround. You should avoid using the PORT_DIS field of the Port 0 Control CSR to initialize the RapidIO IP core receiver.

    This issue will be fixed in a future version of the RapidIO IP core.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices