Article ID: 000073770 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there a way to minimize the initialization time in the legacy RLDRAM II core during simulation when using Stratix II device?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description No, there is no option to minimize the initialization time in the legacy RLDRAM II controller core during simulation for Stratix® II devices.

Related Products

This article applies to 1 products

Stratix® II FPGAs