Back-to-Back RapidIO IP Core Read Transactions Might Time Out Later Than Expected

If a RapidIO IP core that includes an Input/Output Avalon-MM slave Logical layer module transmits multiple back-to-back read transactions on the RapidIO link, and some of those read transactions time out, the IP core might not identify and process the time-out for the later transactions for a long time. This issue occurs when multiple back-to-back read transactions are assigned the same time-out timestamp, and multiple transactions with the same time-out timestamp do not receive a response in the expected time. The IP core recognizes and processes the first few reads that time out, but might not recognize that the later reads have timed out until the free running time-out counter rolls over, approximately four seconds later.

This issue has no workaround.

This issue is fixed in version 13.0 of the RapidIO MegaCore function.