Article ID: 000073737 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Why do I get an error when importing a Quartus II software generated PowerPlay Early Power Estimator (.csv) file into the Stratix IV Early Power Esitimator (EPE) Tool?


  • Quartus® II Subscription Edition
    You may see the following error when you import a Quartus® II software generated PowerPlay Early Power Estimator (.csv) file into the Stratix® IV device family EPE version 9.1SP2 and earlier :

    Line <#>: Invalid Clock Frequency!
    Cell value must be between 0.0 and 600.0
    This is because the upper clock limit in the EPE for the Stratix IV device family is incorrect.
    The maximum core clock frequency limit for Stratix IV devices should be 800MHz, but the EPE is currently limiting it to 600MHz.  You can manually edit the .csv file and change occurances of frequencies greater than 600MHz to a value of 600MHz to prevent lines from being skipped. This will assure the device resource count is imported into the EPE, although the clock frequency will not be accurate.
    The correct frequencies are used in the Quartus II software PowerPlay Power Analyzer tool.

    This is fixed in the 10.1 EPE.

    Related Products

    This article applies to 3 products

    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV E FPGA