Article ID: 000073735 Content Type: Troubleshooting Last Reviewed: 11/18/2017

Qsys Pro Does Not Support VHDL Generation for Synthesis and Simulation

Environment

Bug ID: FB370907;

Quartus Edition

Intel® Quartus® Prime Pro Edition

Version Found: 16.0 Version Fixed: 16.1

FPGA Intellectual Property

Simulation

Version Found: 16.0 Version Fixed: 16.1

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The Quartus^® Prime Pro Edition software\'s Qsys Pro beta feature does not support VHDL generation for synthesis and simulation.

Resolution

Generate your synthesis and simulation files in Verilog.

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