Description
This error, or a similar error with a different phase setting, may be generated in the Quartus® II software versions 10.0 to 10.1 SP1 when implementing the ALTLVDS_TX megafunction under the following conditions:
- The Use external PLL option is enabled.
- The What is the phase alignment of 'tx_outclock' with respect to 'tx_out' option is set to a value other than 0° or 180°.
The only valid settings for this option are 0° or 180° when using the external PLL option in the ALTLVDS_TX megafunction. If you wish to use a phase shift for the tx_outclock other than 0° or 180°, create a fourth clock output port from the external PLL to achieve your desired phase shift.
Beginning with the Quartus II software version 11.0, invalid settings are not displayed in this drop-down list.