Article ID: 000073721 Content Type: Troubleshooting Last Reviewed: 10/06/2014

altera_xcvr_custom:phy_inst|av_xcvr_custom_nr:A5|*|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT

Environment

  • Arria® V FPGAs and SoC FPGAs
  • Arria® V GT FPGA
  • Arria® V GX FPGA
  • Arria® V GZ FPGA
  • Arria® V ST SoC FPGA
  • Arria® V SX SoC FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see the following TimeQuest unconstrained clock when using the Arria® V device transceiver Custom PHY in Quartus® II software version 13.0 and later.

    "*|altera_xcvr_custom:phy_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT"

    Resolution

    It is safe to ignore this unconstrained clock in the Quartus II software.

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