Article ID: 000073715 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the Quartus II software specify an incorrect number of power pins in the pin-out file (.pin) for my Stratix IV design with device migration turned on?


  • Quartus® II Subscription Edition

    The Quartus® II software version 9.0 SP2 pin-out file (.pin) and the Fitter report may incorrectly show the number of power pins (VCCIO, VREF and VCCPD) when you are targeting Stratix® IV E, Stratix IV GX, or Stratix IV GT devices with a migration device specified. In some cases, the power pins for larger device densities may appear as No Connect (NC) in the .pin file and Pin Planner because of their pin functionality in the smaller device densities.

    For example, the EP4SGX230FF35C2X device requires 3 VCCIO pins for I/O banks 7C and 8C. When device migration is turned off, the compilation report pin-out section correctly shows the 3 VCCIO pins. However, if you set EP4SGX110FF35C2X as a migration device, only two VCCIO pins are listed for banks 7C and 8C.  The third required VCCIO pins for banks 7C and 8C are incorrectly shown as NC.

    To properly connect your pins to your PCB, follow these steps:

    1. Use the Migration View in the Pin Planner to show the differences between all of the migration devices in your project. In this view, you may find several NC pins in the Pin Migration Result column that correspond to power pins in some of the migration devices.  
    2. Connect the pins on the board for all power pins across all migration devices. You must connect these pins to the proper power supply on your PCB to support all of the devices in your migration list.

    This problem is fixed in the Quartus II software version 10.0.

    Related Products

    This article applies to 3 products

    Stratix® IV GX FPGA
    Stratix® IV E FPGA
    Stratix® IV GT FPGA



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