Article ID: 000073711 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the minimum pulse width timing specification of the asynchronous clear signal for Cyclone III M9K memory block (TM9KCLR)?

Environment

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Description

The minimum pulse width timing specification of the asynchronous clear signal for Cyclone® III M9K memory block (TM9KCLR) across speed grades are:

 

C6 = 371ps

C7 = 379ps

C8 = 378ps

 

Related Products

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Cyclone® III FPGAs