Article ID: 000073703 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get an error in the Quartus® II software while compiling a Synplify or Synplify Pro version 7.5 VQM netlist for some Verilog designs containing PLLs?


  • PLL

    When synthesizing a MegaWizard®-generated PLL instantiation, Synplify and Synplify Pro version 7.5 can cause the following types of errors to be produced by the Quartus II software:


    Error: Can't implement clock multiplication and clock division parameter values for PLL <Hierarchy path for altpll instantiation>:altpll_component|altpll:<instance name>|pll
    Error: PLL <Hierarchy path for altpll instantiation>:altpll_component|altpll:<instance name>|pll does not require parameter clock switchover
    Error: Can't implement PLL because No combination of counter values of M and the pre-divider N satisfy VCO and PFD ranges, for requested clock synthesis

    A workaround for this problem is available now from Synplicity technical support and the problem is scheduled to be fixed in a future release. If you encounter this issue, please contact Synplicity technical support directly through one of the methods listed on the Synplicity Support site to obtain a workaround.

    The Synplify 7.5 release notes on page 3 describe forward-annotating PLL constraints for Stratix® designs, which helps the Synplify software optimize the design for better timing performance. However, this can generate the errors above for PLL instantiations in Verilog HDL. This is not an issue with the PLL instantiation in VHDL.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs