Description
Due to a problem in the Quartus® II software version 13.0, you may see this error if your Verilog HDL code contains a clock mux whose output connects to both an output pin and internal logic.
Resolution
To work around this problem, create an additional wire so that the output has a different name from the clock that is used internally.
This problem is scheduled to be fixed in a future release of the Quartus® II software.