Article ID: 000073656 Content Type: Troubleshooting Last Reviewed: 07/01/2014

Why does the rx_latency_adj_10g and tx_latency_adj_10g signal descriptions refer to 1g for the Arria V and Stratix V devices in the Altera Transceiver PHY IP User Guide?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a mistake in "Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs" of the Altera® Transceiver PHY IP Core User Guide (PDF) the rx_latency_adj_10g and tx_latency_adj_10g signals refer to 1g for the Arria® V and Stratix® V devices.

    The rx_latency_adj_10g and tx_latency_adj_10g signal signals should only refer to 10g.

    Resolution This problem will be fixed in a future version of the Transceiver PHY User Guide (PDF).

     

     

    Related Products

    This article applies to 6 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V GT FPGA
    Arria® V GX FPGA

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