Intel® Quartus® Prime Software v18.1 has improvements made across the three key areas that designers care about the most—performance1, productivity, and usability. Check out the following new training courses and collateral:
- What's New In Intel® Quartus® Prime Software v18.1 training
- Learn how Quartus automatically adds pipeline registers at user specified locations with the new Latency Insensitive Auto-pipelining video.
- The Intel® Quartus® Prime Pro Edition and Standard Edition Handbooks are now subdivided into more manageable user guides, they can be found on the Support page. You can select the topic of interest to see all the relevant documents associated with that topic.
Auto-Pipelining and Latency Insensitive False Path:
Intel® Quartus® Prime Pro Edition can now automatically add the optimal number of pipe stages to your design in locations that have been marked as “Variable Latency” (i.e. areas where the number of cycles it takes for a signal to pass is not important). This feature can help users achieve a high fmax without unnecessarily increasing the designs resource utilization. To learn more about this feature check out our new demo video.
Hyperflex Optimized Interconnect in Platform Designer:
In v18.1 Platform Designer interconnect IPs have been updated to take advantage of Stratix® 10 Hyperflex architecture. User will now see significant frequency improvements in their Stratix® 10 designs compared to v18.0.
Introducing Fractal Synthesis in Intel® Quartus® Prime Pro Edition
To meet the growing need for utilizing the flexibility of an FPGA for arithmetic acceleration, Intel is introducing Fractal Synthesis - a feature that enables Intel® Quartus® Prime to use FPGA resources to create repetitive dot product structures in a highly efficient way. Fractal Synthesis allows Intel® Quartus® Prime to achieve 20-45% area reduction compared to regular Intel® Quartus® Prime flow. Check out Fractal Synthesis in action with this video.
Continue seeing improvements in compile time for your Intel® Stratix® 10 designs in v18.1 compared to prior releases. Check out the Compile User Guide for additional tips on how to reduce compile times
With Intel® Quartus® Prime Pro Edition Software v18.1, all designs will experience reductions in peak virtual memory requirements as compared to v18.0. All Intel® Stratix® 10 designs will compile in less than 64 GB of memory space.
Stratix® 10 device users can now import the database for a hierarchical block from one release to another. This allows the user to do a timing analysis of a partial reconfiguration region developed in a later release with the place and route results for the static region in a previous release.
In v18.1 Quartus comes with even more optimization option, giving users a choice in improving their design’s routability and performance. Find more information on these different modes in the compiler guide. Additional modes have also been added to the Design Space Explorer.
Updates have been made to the GUI for Clock Tree, Chip Planner and Pin Planner. Users now have more visibility into the clock tree and how the clock tree is synthesized and will see improvements in floor planning capability.
Platform Designer Usability Enhancements:
The Systems Contents Tool will be replaced with a new System View Tool. This tool will allow users to define their project’s hierarchy from a view perspective rather than a design perspective and enables multi-level hierarchy modules interactions within the GUI.
Documentation and Support
Find technical documentation, videos, and training courses for Intel® Quartus®
Prime Design Software.
Product and Performance Information
Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance.