What's New in Intel® Quartus® Prime Software
Power and Performance
Intel® Agilex™ Device Support
The Intel® Quartus® Prime Pro Edition Software v21.1 supports the Intel® Agilex™ device family. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm SuperFin Technology and 2nd Generation Intel® Hyperflex™ FPGA Architecture to deliver up to 45% higher performance (geomean vs. Intel® Stratix® 10)1 or up to 40% lower power.1
The compiler in the Intel Quartus Prime Pro Edition Software is a fast, multi-faceted tool, allowing different compilation strategies that meet the designer’s needs. In addition to standard compilation, which can give you a baseline for performance, there are other compilation options available:
- Fast compile for small designs can be used to get quick compiles at the beginning of the development process when only a small portion of the design has been implemented.
- High-effort compilation is used to make the compiler maximize its effort to get the best performance results out of a design.
- Fast preservation compilations can be used with partitioned designs. Using a previously satisfactory compilation, fast preservation simplifies the logic of a preserved partition to only the interface between the partition boundary and the rest of the design. The use of fast preservation feature reduces the compile time required for the preserved partition and the overall compile time.
- Back Annotation is used in conjunction with seed sweeping to take the best compilation from running different seeds. The best compilation from the run is then used as the starting point for additional seed sweeping after fixing in place the results of pin-placement, clocks, RAMS, digital signal processors (DSPs), or a combination of these. The results are typically higher Fmax with less variation in results. Additionally, a GUI for Back Annotation has been provided to make it even easier to use.
- Engineering Change Order (ECO) compilation is used when only minor changes are needed to an otherwise good compile. ECO compiles can provide a compilation speedup of 5X – 10X.2 It replaces the Rapid Recompile flow for post-fit Signal Tap changes with significant compilation speedup.
Additionally, there are many other parameters available to customize your compilation strategies to meet your specific requirements.
Power and Thermal Calculator
The Power and Thermal Calculator (PTC) supports Intel® Agilex™ and Intel® Stratix® 10 devices. For these devices, it replaces the older Early Power Estimator. It can be used inside the Intel Quartus Prime Pro Edition Software or as a stand-alone tool. The look and feel of the PTC has been improved allowing greater customization of the layout as well as tooltips to describe various parameters in the PTC. A new Thermals tab has been introduced for Intel Agilex devices, which allows you to do thermal analysis for the design and provides a method to obtain cooling solutions under various conditions.
Ease of Use
The Intel Quartus Prime Pro Edition Software continues to expand its rich set of compilation reports. In the v21.1 software release, the following new reports have been added:
- Timing closure summary
- Hierarchical reset
- List clocks in path
- CDC async
This new software version also includes improvements to the following existing reports:
- Pipelining information
- Logic depth
- Neighbor paths
In addition to the new and improved reports, cross-probing between reports is supported in many of them. This expanding portfolio of reports enables you to gather detailed information about routing, congestion, timing, tension, span, routing effort, and many other metrics that will provide rapid feedback for closing timing quickly.
ECO Compilation provides a method to do small changes, such as changing a netlist connection, correcting a LUT logic error, or placing a node in a new location during the design verification stage. The ECO flow typically results in a lower compile time because only the specified ECO changes need to be compiled, leaving the rest of the design unchanged. Enhancements to this flow includes using the ECO compilation flow with the Signal Tap II Logic Analyzer, providing a GUI front-end for the ECO compilation (the fitter toolkit), and additional analysis tools to get the most out of the ECO compilation flow for design verification.
Platform Designer has been enhanced to improve GUI performance in the Intel® Quartus® Prime Pro Edition Software. New features have been added to allow parameter support for HDL and Blackbox IP instantiations as well as the ability to pass parameters via register-transfer level (RTL). The Avalon® Multi-Master Pipeline Bridge now supports passing the writeresponsevalid signal back to the host component. Additionally, the Avalon® Streaming credit flow control, which provides higher performance through source flow control has been updated.
New and updated IP cores targeting high-speed communications, including:
- PCI Express
For more information, visit the Intel® FPGA IP Portfolio page.
Questa*-Intel® FPGA Edition Software (Beta Evaluation)
Intel will be moving to Questa*-Intel® FPGA Edition from Mentor Graphics. Questa*-Intel® FPGA Edition is the core simulation and debug engine of the Questa Verification Solution providing the latest in FPGA simulation technology. Prior to moving from ModelSim*-Intel® FPGA Edition to Questa*-Intel® FPGA Edition, Intel has released this Beta edition. Signups are limited and are on a first come first serve basis. Intel welcomes your feedback on the new simulator.
Documentation and Support
Find technical documentation, videos, and training courses for Intel® Quartus®
Prime Design Software.
Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.
Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure.
Your costs and results may vary.
Benchmarks were done on a suite of 28 designs on an Intel® Stratix® 10 1S280 device with Linux 64 operating system. Comparison is done between the baseline compile time and the ECO compile time after netlist changes (8 – 2000 depending on what was available for ECO changes). Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For general information about performance and benchmark results, visit http://www.intel.com/benchmarks.