Matrix Focused: Accelerators and New CPU Instructions
From the data center to edge devices, AI continues to permeate all aspects of the compute spectrum. To that end, we’ve developed purpose-built accelerators and added microarchitectural enhancements to our CPUs with new instructions to accelerate AI workloads.
An application-specific integrated circuit (ASIC) is a type of processor that are built from the ground up for a precise usage. In most cases, ASICs will deliver best-in-class performance for the matrix compute workloads it was designed to support.
Intel is extending platforms with purpose-built ASICs that offer dramatic leaps in performance for Matrix applications. These include Habana AI processors and the Ponte Vecchio High Performance Compute GPUs with new XMX (Xe Matrix Extensions) technology. Each XMX engine is built with deep systolic arrays, enabling Ponte Vecchio to have significant amounts of both vector and matrix capabilities in a single device.
In addition, Intel® Deep Learning Boost (Intel® DL Boost), available on 3rd Gen Intel® Xeon® Scalable processors and 10th Gen Intel® Core™ processors, adds architectural extensions to accelerate Vector Neural Network Instructions (VNNI). In order to dramatically increase the instructions per clock (IPC) for AI applications, we have introduced a new technology called Intel® AMX (Advanced Matrix Extensions). This technology will first be available as part of our next generation Sapphire Rapids architecture that significantly increases matrix type operations.
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