Intel has recognized 18 leading academic researchers with 2020 Outstanding Researcher Awards (ORAs). From projects such as optimizing spin-to-charge current conversion, to accelerating datacenter FPGAs for deep learning, to evaluating roadway readiness for autonomous vehicles, these Intel and university research collaborations are advancing today’s computing into future technologies.
Intel sponsors and works alongside academic researchers around the globe in areas as quantum computing, artificial intelligence (AI), and other emerging innovative technologies. Intel participates in research initiatives with prominent university science and technology centers, The National Science Foundation, and the Semiconductor Research Corporation.
Annually, Intel recognizes the exceptional contributions made through Intel university-sponsored research with Outstanding Researcher Awards.
“Intel values academic research tremendously. We fund over a thousand worldwide lead academic researchers annually. In selecting the award winners, careful consideration has been given to aspects of the sponsored research such as fundamental insights, technical difficulty, effective collaboration, potential student hiring, and industry relevance particularly to Intel. Hearty congratulations to our 2020 ORA winners,” said Mandy Pant, Director of Intel’s Corporate Research Council that initiates the awards.
The 2020 Intel Outstanding Research Award winners are:
Professor Felix Casanova, CIC nanoGUNE, Spain
Integration of Electrical Magnetic Switching and Spin-to-Charge Conversion in a Nanodevice
Spin-to-charge current conversion based on spin-orbit effects is an essential ingredient to detect spin currents and, in particular, for the realization of Casanova's proposed magneto-electric spin-orbit (MESO) logic. Based on the functionality needed for the MESO logic, such as reading the magnetic state of a single ferromagnet (FM), his team is designing a local device that couples a single FM electrode to the spin-orbit material (SOM) with a T–shaped nanostructure.
Professor Alvin Cheung, University of California, Berkeley, USA
Professor Jonathan Ragan-Kelley, Massachusetts Institute of Technology, USA
Computer Assisted Programming for Heterogenous Architectures (CAPA)
Professors Cheung and Ragan-Kelley are developing ARION, a system for compiling programs onto heterogeneous platforms. The team will use verified lifting, which rewrites legacy code into a clean specification, stripping away optimizations that target legacy architectures. This spec, written in a DSL, can then be compiled to new platforms, sometimes with orders of magnitude of speedup in resulting code performance.
Professor Michael P. Flynn, University of Michigan, USA
Acoustic Beam Forming and Speech Recognition
Flynn's research aims to reduce the energy cost and die area for speech recognition by an order of magnitude. Related to ambient computing efforts with the specific goal of acoustic beam forming to track a specific user, acoustic far field tracking is growing in use and capability. The research goal is to develop a single chip with 8 ADCs, beam former, feature extraction, and neural network, altogether with less than 3mW.
Professor Daniel Gruss, Graz University of Technology, Austria
Information Flow Tracking Across the Hardware-Software Boundary
This project focuses on developing novel approaches for information-flow tracking across the hardware-software boundary. The result will be a principled approach to enforcing end-to-end security properties. The approach rests on three pillars: (1) microarchitecture modeling for security, (2) security contracts between hardware and software, and (3) program analysis and compilation for security.
Professors Debdeep Jena, Huili (Grace) Xing, and Alyosha Molnar, Cornell University, USA
Professor Tomas Palacios, Massachusetts Institute of Technology, USA
Wide-Bandgap pFETs: Materials, Devices, and Circuits
In collaboration with MIT, the Cornell team seeks a high-performance wide-bandgap PMOS solution for use in RF, power electronics, or digital/analog applications. The team looks to provide a holistic pFET solution through materials innovations, device processing, fabrication, and testing, as well as the development of transport and device physics and compact models, circuit models, and demonstration.
Professor Heiner Litz, University of California, Santa Cruz, USA
FoMR: Improving Microprocessor IPC for Data Center Workloads
Litz's research will examine key challenges to improve instructions per cycle (IPC) performance in data center processors. These challenges include learning the complex behavior of data center applications and leveraging the obtained models at execution time with a limited power and transistor budget.
Professor Moinuddin Qureshi, Georgia Institute of Technology, USA
Efficient and Robust Hybrid Memory Architectures
Qureshi will propose and evaluate mechanisms to improve performance of hybrid memory architectures. He will investigate hardware-based page remapping and hybrid tag design for DRAM caches. The research will focus on writeback aware hybrid memory architecture and dynamic memory compression with low metadata overhead.
Professor Visvesh Sathe, University of Washington, USA
Robust, Efficient, Integrated SIMO Voltage Regulation Using a Unified Clock and Power Architecture
Sathe's research seeks to advance the state-of-the-art in the areas of clock-generation and voltage-regulation through a unified clock and power (UnCaP) architecture. This effort will pave the way for highly scalable and robust SoC voltage domain regulation.
Professor Shreyas Sen, Purdue University, USA
Ground-Up Root-Cause-Analysis Guided Low-Overhead Generic Countermeasures for Power and Electromagnetic Side Channel Attacks
The power and electromagnetic (EM) side-channel (SC), which allows extraction of secret keys from unintentional powers signatures/EM emanations, poses a serious threat to security of computing devices. Sen’s research will use EM analysis skills to treat the EM SC source as a “white-box” and pinpoint the critical information leakage sources.
Professors Jae-sun Seo, Yu Cao, and Sarma Vrudhula, Arizona State University, USA
Accelerating Datacenter FPGAs for Deep Learning Training Workloads
The ASU team will investigate FPGA-based accelerator designs for training deep learning algorithms. They aim to develop an automatically compilable, energy-efficient, fine-grain reconfigurable FPGA, which can accelerate the training process with high performance. The team also will investigate energy-efficient large-scale FPGA implementation of backpropagation algorithms for training deep neural networks (DNNs) with low precision and structured sparsity.
Professor Xuesong Wang, Tongji University, China
Evaluation and Simulation of China Roadway Infrastructures Readiness for Autonomous Vehicles
This project is designed to evaluate the roadway readiness or fitness for autonomous vehicles (AVs) with the aim of accelerating their successful deployment. The research will identify the boundaries of AV, such as the kind of roadway designs and traffic environments that are most appropriate for AV’s strategic and tactical operations.
Professor Ali E. Yilmaz, University of Texas at Austin, USA
Reduced‐Domain Layered‐Medium Integral‐Equation Methods for Efficient EM Simulation of Full‐Scale Electronic Packages
This research will enable predictive and fast full-wave simulation of full-scale packages by exploiting the latest developments in computational electromagnetics. Yilmaz will develop reduced-domain layered-medium integral-equation (LMIE) based models targeting densely metallized packages to simplify modeling/meshing, to increase accuracy, and to reduce number of unknowns.