The ability to reconfigure the settings of embedded transceivers is an advantage to today’s FPGA designers. Tasks such as fine-tuning buffer settings and in-system upgrades are made possible. This online training course is an introduction to the transceiver reconfiguration capability found in Altera® 28-nm devices, namely Cyclone® V, Arria® V and Stratix® V device families. It looks at the supported types of transceiver reconfiguration. It then shows how to enable reconfiguration in the Quartus® II software version 12.1 and how to develop logic to control the reconfiguration process.
NOTE: Transceiver reconfiguration in Stratix IV, Arria II and Cyclone IV device families is covered in the online training “Dynamic Reconfiguration in Altera Transceiver Devices”.
At Course Completion
You will be able to:
- Indicate the reconfigurable parts of the high-speed gigabit transceivers
- Design a transceiver reconfiguration controller that will enable you to dynamically control transceiver functionality during device operation
- Background in high-speed digital design
- Working knowledge of the FPGA design flow using the Quartus II software
- Familiarity with the architecture of Cyclone V, Arria V and Stratix V devices, particularly the embedded high-speed transceivers
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
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