Implementing the Triple-Speed Ethernet MegaCore Function (OTSE1116P2)

24 Minutes Online Course

Course Description

This online course will instruct you in how to build 10/100/1000 Mb Ethernet solutions targeting Altera® transceiver devices using the Quartus® II software. In this course, you will learn how to configure the Altera Triple Speed Ethernet (TSE) MegaCore® IP function for your Ethernet-based design and how to connect it to the system interconnect fabric using the Qsys system building tool. Lastly, you will investigate how the embedded transceivers are configured to support Gigabit Ethernet.

At Course Completion

You will be able to:

  • Configure a stand-alone TSE MegaCore implementation and incorporate it into a design
  • Incorporate a TSE component into a Qsys system
  • Configure the transceiver for a custom Ethernet MAC solution

Skills Required

  • Understanding of the Ethernet technology specifications
  • Familiarity with common high-speed transceiver architecture OR viewing the following course: Transceiver Basics
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software
  • Some familiarity with Qsys

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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