Timing Closure Using Timing Analyzer Custom Reporting (OTIM1100)

21 Minutes Online Course

Course Description

Learn how to use the Intel® Quartus® Prime Timing Closure Recommendations reporting in Timing Analyzer to help you find issues that may be causing timing failures.

At Course Completion

You will be able to:

  • Use the Timing Closure Recommendation custom reporting feature in Timing Analyzer to close timing on your designs
  • Identify HDL code changes needed to address timing issues
  • Change Intel Quartus Prime software settings to address timing issues

Skills Required

  • Background in digital logic design
  • Basic understanding of Verilog HDL or VHDL coding
  • An understanding of basic FPGA design flow
  • Basic understanding of the Intel Quartus Prime user interface
  • Basic understanding of Timing Analyzer

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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