Timing Closure Using Timing Analyzer Custom Reporting (OTIM1100)

Course Description

Learn how to use the Intel® Quartus® Prime Timing Closure Recommendations reporting in Timing Analyzer to help you find issues that may be causing timing failures.

At Course Completion

You will be able to:

• Use the Timing Closure Recommendation custom reporting feature in Timing Analyzer to close timing on your designs
• Identify HDL code changes needed to address timing issues
• Change Intel Quartus Prime software settings to address timing issues

Skills Required

• Background in digital logic design
• Basic understanding of Verilog HDL or VHDL coding
• An understanding of basic FPGA design flow
• Basic understanding of the Intel Quartus Prime user interface
• Basic understanding of Timing Analyzer

Prerequisites

We recommend completing the following courses:

• Timing Analyzer: Introduction to Timing Analysis
• Using the Intel® Quartus® Prime Standard Edition Software: An Introduction
• Verilog HDL Basics
• VHDL Basics

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Introduction to Parallel Computing with OpenCL™ on FPGAs

Related Courses

Below are the related courses you may be interested in:

• Migrating to the Quartus Prime Pro Edition Software

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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