Are you trying to improve the signal integrity of your Intel® Arria® 10 FPGA high-speed serial transceiver links? This training introduces you to the Transceiver Toolkit found in the Intel® Quartus® Prime software v. 15.1 & shows you how to use it to optimize your high-speed channel’s transmitter & receiver analog settings. Learn how to enable toolkit support in a design and then connect to transceiver channel buffers & dynamically perform various link tests.
This training specifically covers the Intel Arria 10 family, but may also be applied to the Intel Cyclone® 10 GX FPGA family. For Cyclone® V, Arria V & Stratix® V devices, see the online training, Transceiver Toolkit for 28-nm Devices.
At Course Completion
You will be able to:
- Enable Transceiver Toolkit support in your own Intel Arria 10 or Cyclone 10 GX FPGA design
- Setup and launch the Transceiver Toolkit to perform a high speed link test
- Perform BER testing using the Auto Sweep feature in the toolkit
- Select the best analog settings to optimize the signal integrity of your transceiver link
- Basic knowledge of the Intel Quartus Prime software
- General understanding of FPGA architecture including transceiver architecture
- General understanding of transceiver reconfiguration concepts
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: