Transceiver Toolkit for 28-nm Devices (OTCVR1100)
Course Description
Are you trying to improve the signal integrity of your transceiver links? This can be a challenge with the multi-gigabit interfaces used in FPGA designs. This training introduces the Transceiver Toolkit found in the Intel® Quartus® Prime software v. 15.1 & shows how to use it to optimize your high-speed channel’s transmitter & receiver analog settings. Learn how to build a design so that you can connect to its transceiver channel buffers & perform various link tests. Using Transceiver Toolkit features like Auto Sweep & EyeQ, you can verify & potentially improve the Bit Error Rate (BER) of your system.
This training covers Cyclone® V, Arria® V & Stratix® V device families. For Intel Arria 10 devices, see the training Transceiver Toolkit for Intel Arria 10 Devices.”
At Course Completion
You will be able to:
- Download a Cyclone V, Arria V or Stratix V design example to perform link tests or incorporate Transceiver Toolkit support into your own design
- Setup and launch the Transceiver Toolkit to perform a high speed link test
- Perform BER testing using the Auto Sweep and EyeQ features in the toolkit
- Select the best analog settings to optimize the signal integrity of your transceiver link
Skills Required
- Basic knowledge of the Intel Quartus Prime software including the Platform Designer tool
- General understanding of FPGA architecture including transceiver architecture
- General understanding of transceiver reconfiguration concepts
Prerequisites
We recommend completing the following courses:
- Introduction to Platform Designer
- The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
- The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
- Transceiver Basics for 20 nm and 28 nm Devices
- Using the Intel® Quartus® Prime Standard Edition Software: An Introduction
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: