Synplify Synthesis Techniques with the Quartus II Software (Legacy Course) (OSYN1150)

30 Minutes Online Course

Course Description

You will learn how Megafunctions are processed in Synplify and constraints forward annotated to the Quartus® II software. You will learn about Fast Synthesis and Automatic Compile Points (ACP) flows to improve turnaround times in your design. You will learn about a graphical timing correlation tool to compare timing paths in Synplify and the Quartus II software. You will also learn about new mapping features for RAMs and DSPs in the Stratix® V family. Finally, you will be introduced to the integration of Synopsys VCS waveform viewer with Synplify Analyst viewer, Synopsys Formality verification support, as well as DesignWare® intellectual property blocks.

At Course Completion

You will be able to:

  • Use the cross-probing feature in Analyst to analyze and debug circuits
  • Understand how MegaWizard™ Plug-Ins and MegaCore® functions are processed and used in your Synplify design
  • Understand new direct mapping feature for RAMs/DSPs in Stratix V devices
  • Use Automatic Compile Points to invoke Incremental Compilation in the Quartus II software
  • Analyze timing correlation graphically

Skills Required

  • Background in digital logic design

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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