Creating Second Stage Bootloader for Altera SoCs (OSOCSSBL)

Course Description

This course discusses how to use the tools and features available in the Altera® SoC Embedded Design Suite to successfully customize and generate a second stage bootloader for ARM®-based SoC devices. We will talk specifically about the flow and the tools necessary to quickly generate a customized second stage bootloader. We will cover both the preloader which is the Arria® V and Cyclone® V version of the second stage bootloader as well as the U-Boot bootloader which is the Arria 10 version of the second stage bootloader.

At Course Completion

You will be able to:

• Understand the flow and tools available to quickly customize and generate the second stage boot software
• Be able to generate a preloader image for Cyclone V and Arria V SoCs
• Be able to generate a bootloader image for Arria 10 SoCs

Skills Required

• Basic software development knowledge
• Understanding of SoC Boot Flow

Prerequisites

We recommend completing the following courses:

• Hardware Design Flow for an Arm*-based Intel® SoC FPGA
• Software Design Flow for an Arm*-based Intel® SoC FPGA

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Customizing Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX FPGA Hard IP for PCI Express*

Related Courses

Below are the related courses you may be interested in:

• Intel® SoC FPGA Bare-metal Programming and Hardware Libraries (Legacy Course)
• SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals
• SoC Hardware Overview: the Microprocessor Unit

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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