Secure Boot with Arria 10 SoC FPGAs (OSOCSECBOOT)

17 Minutes Online Course

Course Description

This course discusses the secure boot options available with the Arria® 10 SoC FPGAs with the ARM®-based hard processing system (HPS). We will talk about the tools and methodology necessary to implement an authenticated and/or encrypted bootloader. We will explore the components of the Arria 10 SoC FPGA that allows for authentication and decryption. We will cover various tools, as part of the SoCEDS or Quartus® Prime tool, that can be used to generate keys and produce secure boot images.

At Course Completion

You will be able to:

  • Generate a signed boot image
  • Generate an encrypted boot image
  • Understand the Arria 10 SoC FPGA features that authenticates and decrypts a secure boot image
  • Use the various tools available in the Quartus Tools and the SoC EDS to generate and program the device with an encrypted and/or signed second stage boot image.

Skills Required

  • Basic software development knowledge

Prerequisites

We recommend completing the following courses:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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